Semiconductor manufacturers face a constant challenge to comply with Moore's Law. They constantly strive to continually decrease feature sizes, such as sizes of active and passive devices, interconnecting wire widths and thicknesses, and power consumption as well as increase device density, wire density and operating frequencies. These smaller electronic components also require smaller packages that utilize less area than packages of the past, in some applications.
Three dimensional integrated circuits (3DICs) are a recent development in semiconductor packaging in which multiple semiconductor dies are stacked upon one another, such as package-on-package (PoP) and system-in-package (SiP) packaging techniques. Some methods of forming 3DICs involve bonding together two or more semiconductor wafers/dies, and active circuits such as logic, memory, processor circuits and the like located on different semiconductor wafers/dies. The commonly used bonding techniques include direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermo-compressive bonding, reactive bonding and/or the like. Once two semiconductor wafers/dies are bonded together, the interface between two semiconductor wafers/dies may provide an electrically conductive path between the stacked semiconductor wafers/dies.
One advantageous feature of stacked semiconductor devices is that much higher density can be achieved by employing stacked semiconductor devices. Furthermore, stacked semiconductor devices can achieve smaller form factors, cost-effectiveness, increased performance and lower power consumption.